1. Field of the Invention
The illustrative embodiments relate to data processing systems for physical synthesis of semiconductor devices. More particularly, the illustrative embodiments relate to a set of pin-based constraints for detailed placement that may streamline the wire length reduction process without degrading device timing.
2. Description of the Related Art
Physical synthesis is the process in which a semiconductor device is taken from the list of components and connections, called a netlist, to a geometrical layout of the device. Global placement is one of the critical processes in physical synthesis. The task of global placement is to determine the overall locations of standard cells in a semiconductor device design. After global placement, the design is typically optimized with respect to device timing.
However, transforms may be performed to reduce the weighted total wire length (WTWL) of the device. During each transform, the module may recursively move one or multiple cells according to transform guidelines. The placement of the cells after these moves may not be legal, thus the transform may also need to legalize the placement by sliding cells along the circuit row. After legalization, the transform has produced a new legal placement.
A detailed placement module performs transforms to convert cell placement from one location to another location within the device. These transforms may insert new cells or change the size of existing cells. The transforms are generally an iterative process performing a series of incremental move steps. Placement changes may result in overlaps between cells. Legalization algorithms have been developed to remove the cell overlaps. Legalization algorithms are designed to minimize the disturbance to the original placement. Therefore, these transforms take a legally placed netlist and change locations of cells while still maintaining legality.
The typical legalization algorithm may result in some wire length degradation. In addition, the relative order of newly inserted or resized cells, are not fully optimized. These transforms only check whether the movements reduce the total wire length. Some detailed placement techniques may help reduce wire length but typically, these techniques also degrade the timing that was previously optimized by physical synthesis. In addition, reducing total wire length may not result in a timing improvement of the overall device. There may be no timing improvement because detailed placement may increase the wire length on critical paths while reducing the total wire length.
Detailed placement transforms may also violate electrical constraints. Electrical constraints are comprised of slew limits and capacitance limits. Slew limits define the maximum slews permissible on all nets of the design. Slew is a value representing the maximum rate of change of signal at a gate output. Capacitance limits define the maximum effective capacitance that a gate or an input pin may drive. Violations of these rules, referred to as slew violations and capacitance violations taken together are called electrical violations. The time involved in re-optimization of electrical parameters and wire length may add significantly to the overall design flow cycle time.